The present invention relates to the manufacturing of semiconductor devices, and more particularly, to copper and copper alloy metallization in semiconductor devices.
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing sub-micron-sized, low resistance-capacitance (RC) metalization patterns. This is particularly applicable when the sub-micron-features, such as vias, contact areas, lines, trenches, and other shaped openings or recesses have high aspect ratios (depth-to-width) due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, usually of doped monocrystalline silicon (Si), and a plurality of sequentially formed inter-metal dielectric layers and electrically conductive patterns. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns of vertically spaced metalization levels are electrically interconnected by vertically oriented conductive plugs filling via holes formed in the inter-metal dielectric layer separating the metalization levels, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise five or more levels of metalization to satisfy device geometry and microminiaturization requirements.
A commonly employed method for forming conductive plugs for electrically interconnecting vertically spaced metalization levels is known as xe2x80x9cdamascenexe2x80x9d-type processing. Generally, this process involves forming a via opening in the inter-metal dielectric layer or interlayer dielectric (ILD) between vertically spaced metalization levels which is subsequently filled with metal to form a via electrically connecting the vertically spaced apart metal features. The via opening is typically formed using conventional lithographic and etching techniques. After the via opening is formed, the via is filled with a conductive material, such as tungsten (W), using conventional techniques, and the excess conductive material on the surface of the inter-metal dielectric layer is then typically removed by chemical mechanical planarization (CMP).
A variant of the above-described process, termed xe2x80x9cdual damascenexe2x80x9d processing, involves the formation of an opening having a lower contact or via opening section which communicates with an upper trench section. The opening is then filled with a conductive material to simultaneously form a contact or via in contact with a conductive line. Excess conductive material on the surface of the intermetal dielectric layer is then removed by CMP. An advantage of the dual damascene process is that contact or via and the upper line are formed simultaneously.
High performance microprocessor applications require rapid speed of semiconductor circuitry, and the integrated circuit speed varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases, in accordance with submicron design rules, the rejection rate due to integrated circuit speed delays significantly reduces manufacturing throughput and increases manufacturing costs.
One way to increase the circuit speed is to reduce the resistance of a conductive pattern. Conventional metalization patterns are typically formed by depositing a layer of conductive material, notably aluminum (Al) or an alloy thereof, and etching, or by damascene techniques. Al is conventionally employed because it is relatively inexpensive, exhibits low resistivity and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the submicron range, step coverage problems result from the use of Al. Poor step coverage causes high current density and enhanced electromigration. Moreover, low dielectric constant polyamide materials, when employed as inter-metal dielectric layers, create moisture/bias reliability problems when in contact with Al, and these problems have decreased the reliability of interconnections formed between various metalization levels.
One approach to improved interconnection paths in vias involves the use of completely filled plugs of a metal, such as W. Accordingly, many current semiconductor devices utilizing VLSI (very large scale integration) technology employ Al for the metalization level and W plugs for interconnections between the different metalization levels. The use of W, however, is attendant with several disadvantages. For example, most W processes are complex and expensive. Furthermore, W has a high resistivity, which decreases circuit speed. Moreover, Joule heating may enhance electromigration of adjacent Al wiring. Still a further problem is that W plugs are susceptible to void formation, and the interface with the metalization level usually results in high contact resistance.
Another attempted solution for the Al plug interconnect problem involves depositing Al using chemical vapor deposition (CVD) or physical vapor deposition (PVD) at elevated temperatures. The use of CVD for depositing Al is expensive, and hot PVD Al deposition requires very high process temperatures incompatible with manufacturing integrated circuitry.
Copper (Cu) and Cu-based alloys are particularly attractive for use in VLSI and ULSI semiconductor devices, which require multi-level metallization. Cu and Cu-based alloy metalization systems have very low resistivities, which are significantly lower than W and even lower than those of previously preferred systems utilizing Al and its alloys. Additionally, Cu has a higher resistance to electromigration. Furthermore, Cu and its alloys enjoy a considerable cost advantage over a number of other conductive materials, notably silver (Ag) and gold (Au). Also, in contrast to Al and refractorytype metals (e.g., titanium (Ti), tantalum (Ta) and W), Cu and its alloys can be readily deposited at low temperatures formed by well-known xe2x80x9cwetxe2x80x9d plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with the requirements of manufacturing throughput.
Another technique to increase the circuit speed is to reduce the capacitance of the inter-metal dielectric layers. Dielectric materials such as silicon oxide (SiO2) have been commonly used to electrically separate and isolate or insulate conductive elements of the integrated circuit from one another. However, as the spacing between these conductive elements in the integrated circuit structure has become smaller, the capacitance between such conductive elements because of the dielectric being formed from silicon oxide is more of a concern. This capacitance negatively affects the overall performance of the integrated circuit because of increased power consumption, reduced speed of the circuitry, and cross-coupling between adjacent conductive elements.
A response to the problem of capacitance between adjacent conductive elements caused by use of silicon oxide dielectrics has led to the use of other dielectric materials, commonly known as low-k dielectrics. Whereas silicon oxide has a dielectric constant of approximately 4.0, many low-k dielectrics have dielectric constants less than 3.5. Examples of low-k dielectric materials include organic or polymeric materials. Another example is porous, low density materials in which a significant fraction of the bulk volume contains air, which has a dielectric constant of approximately 1. The properties of these porous materials are proportional to their porosity. For example, at a porosity of about 80%, the dielectric constant of a porous silica film, i.e. porous SiO2, is approximately 1.5. Still another example of a low-k dielectric material is carbon doped silicon oxide wherein at least a portion of the oxygen atoms bonded to the silicon atoms are replaced by one or more organic groups such as, for example, an alkyl group such as a methyl (CH3 xe2x80x94) group.
FIG. 8 depicts a cross-section of a metal interconnect portion formed in accordance with prior art methods of processing. On a substrate 110 a bottom etch stop layer 111 is formed. The bottom etch stop layer 111 may be made of a number of different materials, such as silicon nitride or silicon carbide. The thickness of the bottom etch stop layer 111 is typically greater than 500 Angstroms in order to provide sufficient etch stop capability. Besides being a diffusion barrier for substrate 110, the bottom etch stop layer 111 serves to protect the substrate 110 from damage during the dielectric layer etching process.
A first dielectric layer 112, which may comprise low k dielectric material, is formed over the bottom etch stop layer 111. A middle etch stop layer 114, which may comprise silicon nitride or silicon carbide, for example, is formed on the first dielectric layer 112. The thickness of this layer 114 is also normally greater than 500 Angstroms in order to provide sufficient material to protect the underlying first dielectric layer 112. The pattern of a via is formed in the middle etch stop layer 114. A second dielectric layer 116 is then formed on top of the patterned middle etch stop layer 114. Using conventional lithography and etching techniques, the second feature is etched in the second dielectric layer 116. This second feature may be a trench, for instance. The etching continues through the pattern opening in the middle etch stop layer 114 and through the first dielectric layer 112, stopping on the bottom etch stop layer 111. Following the etching of the first and second dielectric layers 112, 116, the bottom etch stop layer 111 is removed from within the via opening, thereby exposing the substrate 110. Conductive material is then filled within the openings created in the first and second dielectric layers 112, 116 to form a conductive line 118 connected to a conductive via 120. The conductive material may be copper or a copper alloy, for example. When copper is used, typically a barrier metal and a seed layer are deposited prior to the deposition of the copper.
One of the problems associated with the above-described processes and structure in the prior art is the limited choices of material for the metal etch stop layer, layer 114 in FIG. 8. The material needs to be etch resistant. A very commonly used material as an etch stop is silicon nitride, which has a dielectric constant of about 7.0. However, the use of a thick etch stop layer of silicon nitride, needed to ensure that the etching will stop on the middle etch stop layer, partially negates the benefits sought by the use of low k dielectric material. This is due to the increased combined capacitance of the etch stop layer and the dielectric layer. The same reasoning holds true for the bottom etch stop layer, layer 111 in prior art FIG. 8. Lower k materials tend to require even greater thicknesses, due to their relatively poor etch resistance qualities. Hence, the use of moderate k materials as etch stop layers mitigate the advantages achieved by low k dielectric materials.
There is a need for a method of forming a middle etch stop layer in damascene processes without requiring another material to be deposited on the dielectric layer to a thickness that overly increases the overall k value.
This and other needs are met by embodiments of the present invention which provide an interconnect arrangement comprising a dielectric layer having a lower portion of untreated dielectric material, and an upper portion of treated dielectric material. The upper portion exhibits greater etch resistance than the lower portion to the same etchant chemistry.
The use of a dielectric layer that contains an upper portion of treated (e.g., carbonized or nitrided) dielectric material allows an interconnect arrangement to be formed without the use of a separate, additional etch stop material to be deposited. In addition to reducing the number of deposition steps, the present invention allows the overall k value of the interconnect arrangement to be lowered, since typical etch stop materials have higher k values than low k dielectric materials.
The earlier stated needs are also met by embodiments of the present invention which provide a method of forming an interconnect arrangement comprising the steps of forming a first dielectric layer having an upper surface and treating the upper surface of the first dielectric layer to form etch stop material. A second dielectric layer is deposited on the treated upper surface of the first dielectric layer. A feature is etched into the second dielectric layer, with the etching stopping on the etch stop material.
The treating of dielectric material may be achieved, in certain embodiments of the invention, by exposing the dielectric material to a carbon-rich plasma at low power. This creates an etch stop layer that has a low k value, and also avoids the need for depositing a different material on the low k dielectric layer. In other embodiments, a nitrogen-rich plasma is provided that nitrides the upper surface of the dielectric layer to alter its etch characteristics.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.